1. Field of the Invention
The present invention relates to an automatic wiring method for a semiconductor package by use of a CAD system, wherein bonding pads to be connected to semiconductor chips and vias around the bonding pads are disposed on a virtual plane, and a wiring pattern is formed by connecting the bonding pads to the vias.
2. Description of the Related Art
In the case of designing a wiring pattern of a semiconductor package like a PBGA (Plastic Ball Grid Array) or a EBGA by using the CAD system, the designing is carried out such that bonding pads (for example, wire bonding pads) to be electrically connected to electrode terminals of semiconductor chips (to be called a xe2x80x9cchip padxe2x80x9d) are connected with vias (land parts) that are disposed around the bonding pads, or the vias are connected to each other, on a virtual memory (virtual plane).
In general, the wiring for a printed circuit board (PCB) is arranged linearly in most cases, combined with a multi-wiring structure of a substrate. In most cases, the wiring is turned 90 degrees or 45 degrees at some portions.
On the other hand, in the case of a wiring in a semiconductor package, the wiring is arranged radially from die pads provided at the center of a substrate toward vias (lands) disposed relatively irregularly at peripheral portions. A die pad and a via are connected on a one-to-one basis.
Therefore, it is difficult to apply the wiring logic of the printed wiring substrate (PCB) straight to the designing of a wiring pattern for a semiconductor package. Particularly, in the case of a PBGA, gates are usually provided for sealing semiconductor chips with a resin on the substrate. Thus, the positions of vias (lands) tend to be irregular.
A general procedure of designing the wiring for a semiconductor package using the CAD system will be explained below.
The wiring is designed for each layer both when a substrate of a semiconductor package is wired in a single layer or is wired in multi-layers. The wiring is arranged as follows.
First, a designer determines the outline of a semiconductor package on the virtual plane, and determines the layout of lands (vias) on which connection terminals are formed, by using the CAD system.
Next, an outline of die pads for mounting semiconductor chips thereon is formed. Around the die pads, bonding pads are disposed optionally in a linear shape, or in zigzag pattern, or in the form of an arch.
Next, the bonding pads are connected to chip pads for semiconductor chips.
Next, each bonding pad is wired with each via (land), or a via is wired with another via, after determining each wiring route such that the wires do not cross each other. For example, in the case of a flip-chip connection, the wiring is arranged such that a wire passes through between a chip terminal connection and a via (land).
In general, lines and spaces between via parts (land parts) are calculated, and wiring routes are determined to satisfy a design rule. Then, wiring is simultaneously arranged from all of the bonding pads to the vias (lands). However, after this wiring, it may be necessary to design the wiring again in order to correct deviations in the wiring or in the positions of the vias (lands).
As a method developed for designing wiring for a semiconductor package, there is called the even-space method. In this method, automatic wiring is carried out using circular arcs and line segments on a CAD system, for example. Then, wiring or a positional deviations are corrected by increasing the width of a line segment or by making the intervals between wires (line and space) between the via parts uniform to some extent.
According to this method, concentric circles are drawn at equal intervals around vias, and a tangent line is drawn between specific concentric circles, thereby to automatically determine a wiring route between adjacent vias. Thereafter, deviations or concentration of wiring occurring as a result of the automatic wiring are corrected.
Once a designer has provisionally wired between the bonding pads and the vias (lands), the designer corrects intervals between the wires or positional deviations of the vias (lands). According to this method, it is not possible to limitlessly change the positions of the vias, and it is difficult to change the wiring positions in actual practice. As a result, it is sometimes necessary to design the wiring again.
Further, an attempt to simultaneously realize both the determination of wiring routes and the checking of whether the intervals between the wires satisfy the design rule or not makes the system complex. Therefore, there has been a problem in that it is difficult to expand or change the system, with a result that it is difficult to obtain a satisfactory wiring result.
The even-space method is relatively effective when the vias (lands) to be formed on the substrate of the semiconductor package are formed regularly at equal intervals. However, in actual practice, vias differ, depending on the specifications of the semiconductor package, and they result in irregular layout patterns in many cases. In particular, when surplus vacant space is formed around the vias, the wiring tends to become redundant or unbalanced.
In this case, it is necessary to carry out the wiring again by increasing the radius of a concentric circle of a via where the intervals between the wires are small. Alternatively, it is necessary to disconnect a circular arc and connect wires again, or to move the wires to other spaces. Such correction requires labor and time, and the advantages of automatic wiring cannot be enjoyed. Furthermore, wiring connection errors can easily occur.
It is an object of the present invention to provide an automatic wiring method for a semiconductor package which enables designing of the wiring for a semiconductor package at high speed with reduced labor, by executing a provisional wiring processing for provisionally determining only wiring routes separate from the execution of a wiring formation processing for carrying out the wiring again so that the provisionally-wired wiring routes satisfy a design rule.
In order to achieve the above object, according to one aspect of the present invention, there is provided an automatic wiring method for a semiconductor package using a CAD system, wherein bonding pads to be connected to semiconductor chips and vias around the bonding pads are disclosed on a virtual plane, and forms a wiring pattern by connecting the bonding pads to the vias.
This method comprises: a provisional wiring step for sequentially specifying a first line of the terminal to an n-th line of the terminal, from the innermost periphery to the outermost periphery, of the bonding pads, connecting the bonding pads to predetermined vias present on the specified line of the terminal with line segments, and provisionally determining a wiring route for each line of the terminal such that the line segment passes through between the vias at equal intervals; and a wiring formation step for forming the wiring based on a design rule such that the wiring pattern passes through between the lines of the terminals with uniform intervals between wires based on the provisionally wired wiring routes.
The provisional wiring step comprises:
a first step for specifying the first line of the terminal at the innermost side of the bonding pads, connecting some of the bonding pads to predetermined vias present on the specified first line of the terminal with line segments, drawing line segments from the rest of the bonding pads to a space between the vias such that the end points of the line segments are disposed at equal intervals, thereby to form the wiring routes using line segments that do not cross each other;
a second step for changing the positions of vias to correct deviations, when there are deviations in the wiring routes that pass through between the vias in the first line of the terminal; and
a third step for sequentially specifying lines of the terminals after the first line of the terminal, connecting some of the vias present on the corresponding line of the terminal to some of the vias or the end points of the line segments present on the line of the terminal next to the corresponding line of the terminal, further drawing line segments from the rest of the vias or the end points of line segments other than the corresponding vias or the line segments to a space between vias present on the line of the terminal such that the end points of the line segments are disposed at equal intervals, thereby to form wiring routes with line segments that do not cross each other, and changing the positions of via parts to correct deviations, when there is a deviation in the wiring route that passes through between certain vias in any line of the terminal,
thereby to provisionally determine the wiring routes from the bonding pads to the outmost line of the connection terminal by drawing the line segments.
The wiring formation step comprises:
a step for drawing concentric circular arcs around each via by setting a clearance (a gap) based on a design rule, by using the provisionally wired wiring routes from the bonding pads to the outermost vias, and forming a wiring pattern by drawing tangential lines between the circular arcs where the provisionally wired line segments cross the circular arcs and between the circular arcs and the vias where the circular arcs cross the vias;
a step for drawing a circular arc for modification by taking into account the distance between vias when a deviation has occurred in the wiring pattern that passes through the vias, and connecting the circular arc for modification to the tangent line;
and a step for correcting the wiring pattern, according to need, by changing the shape of a connection portion between the tangent line and the circular arc for modification with a line segment for modification having a length about one to three times the wiring width.